This invention relates to manufacturing processes of a highly integrated semiconductor device, and more particularly to a method of manufacturing a contact of a highly integrated semiconductor device using a self-aligned contact structure which is a relatively simple process.
The area occupied by a unit cell decreases as integration of the semiconductor device increases. Accordingly, in order to reduce the area occupied by a cell, width of a word line and a bit line and space between lines must be reduced further. However, in the highly integrated devices such as 64M DRAM (Dynamic Random Access Memory) which has design rule of 0.4 .mu.m or less, maximum permissible line space is very small and, thus, the formation of a bit line contact or a contact for the storage node using conventional direct contact methods is not as easy as it appears.
That is why most manufacturers use a self-aligned contact method. However, even if this method is used, an etching process becomes very difficult because an aspect ratio increases drastically during a contact etching process as integration of the device increases. Also, problems such as short between the word line and bit line or between the bit line and the charge storage node as well as breaking of the wiring metal line occur. Furthermore, the resistance increases at this time.